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any and all sanyo products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft? control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo representative nearest you before using any sanyo products described or contained herein in such applications. sanyo assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges,or other parameters) listed in products specifications of any and all sanyo products described or contained herein. cmos ic 4-bit single chip microcontroller with eprom ordering number:enn * 2928a LC66E516 sanyo electric co.,ltd. semiconductor business headquarters tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110-8534 japan o2501tn (kt)/71595ha/0268ta(ki) no.2928?/18 preliminary overview the LC66E516 is a 4-bit single-chip microcontroller with an eprom on-chip, and can be used for developing and evaluating application programs for the lc665xx series 4-bit single-chip microcontrollers. the LC66E516 microcontroller is a 4-bit single-chip ic with an eprom on-chip and brought to you in ceramic dic64s package with a window and ceramic qfc64 pack- age with a window. this window permits the user to erase eprom program data as many times as he or she wants. then, it could be said that this single-chip ic is best suited for developing application programs. the LC66E516 microcontroller has the same function and the pin assignment as those of the 4-bit single-chip mask programmed rom-version LC66E516 microcontroller. the on-chip eprom is 16k bytes in size. features ?optional functions user-selectable by speciflying eprom option data. the 56 optional functions on the lc665xx series single- chip microcontrollers can be selected by writing appro- priate data to the on-chip eprom. this function specifi- cation by the user allows application system to be devel- oped and tested under the same working environment as that of production chip. in other words, the same inter- face circuit functions as those of production chips can be built up by the user. please note that the above-mentioned optional functions include port output type(open-drain or pull-up), output pin logic level at reset, watchdog timer selection and the like. ?on-chip 16kb eprom the on-chip eprom enable the user to develop and evalu- ate application programs which can be run on every lc665xx series microcontroller. please note that the lc665xx series microcontrollers are lc66506b, lc66508b, lc66512b, lc66516b, lc66556a, lc66558a, lc66562a, lc66566a, lc66556b, lc66558b, lc66562b, lc66566b and that they are listed in the table on page 18 with a few pieces of information. ?write/read operation with an eprom writer used with the dedicated writer board (w66e516dh for dic, w66e516qh for qfc), an eprom writer avail- able on your local market permits the user to write or read data to or form the 16kb on-chip eprom. please note that the eprom writer should be an advantest prod- uct or the eva800/850 accessory writer used for the 27128 type eprom. ?pin-compatible with a mask programmed rom-version single-chip microcontroller (lc66516b, for example) ?instruction cycle time:0.92 s to 10 s ?single +5v power supply (ta=10 c to 40 c)
LC66E516 no.2928 2/18 notes on evaluation of user application programs for the lc66506, lc66508, lc66512, lc66556, lc66558, lc66562, microcontrollers the above six mask programmed rom-version microcontrollers are equipped with different roms in size from that of the LC66E516 microcontroller. therefore, the following things should be taken into consideration when you are to make an access to the rom on the LC66E516 microcontroller. first, it should be kept in mind that the last 8 addresses between 3ff8 and 3fff are used by the user in order to specify functional option data. this 8-byte area is called option specification area. this option specification area must be exclu- sively used for storing function option data. the option specification will be discussed in detail later in this catalog. as far as the cross assembler to be employed is concerned, the user should use the one for the lc66516 microcontroller. in addition, when you write your user application program, you cannot make any access to addresses beyond the area of a mask programmed rom. such addresses cannot exist anywhere on mask programmed rom-version microcontrollers. to avoid such an illegal access to those nonexistent area, it is recommended that jump (or branch) operations with a jmp instruction and so on be used in your user application program. furthermore, please write "0" to the area beyond that of a mask programmed rom. in this case, needless to say, the last 8 addresses of the eprom should be excluded from the "0" padding. when evaluating the lc66506, lc66508, lc66556, lc66558, do not use the sb instruction. program protection from exposure to light exposure to light will destroy the precious eprom data that you have entered with much labor. in order to protect them, it should be strongly recommended that the eprom window should be covered with an opaque label while you are at work with the eprom. for the LC66E516/p516, if the res is set to "l" level during the hold mode (hold=l), be sure to change the hold level from "l" to "h" and then change the res level from "l" to "h" when releasing the hold mode. usage notes the LC66E516 single-chip ic is intended for use by those who are in charge of the development and evaluation of appli- cation programs for the lc665xx series 4-bit single-chip microcontrollers. please keep in mind the following when the user application developers are to work with this single-chip microcontroller. notes on LC66E516 internal operations after reset as the figure shows, the LC66E516 microcontroller starts normal program execution at least 3 instruction cycles later after the oscil- lation by the osc function block becomes stable. in other words, the res pin level (active low) must be active for at least 3 instruc- tion cycles after the oscillation becomes stabilized. as the figure also shows, the oscillation stabilization requires more than 10 milli- seconds. it is also shown that option data setting requires 8 instruc- tion cycles after the res pin level changes to the inactive level (or to v ih voltage level). after all those operations are carried out, the LC66E516 microcontroller starts program execution normally from address 0 in the eprom (that is, the content at address 0 is auto- matically set in the program counter (pc)). at this point, please note that port output type will be open-drain, not pull-up output type, as long as the res pin stays active.
LC66E516 no.2928 3/18 option-specified output type ffo h is set. 4.0v to 6.0v/0.92 to 10 s (tool:5v 5%) 30 to +70 c 2.5ma max.(4mhz ceramic resonator oscillation) 3.5ma max.(4mhz external clock source) 2.5ma max.(3mhz typ.rc oscillation) (tool:evaluation impossible) lc6655x series 65536 cycles approx. 64ms at 4mhz (tcyc=1 s) 16384 cycles approx. 32ms at 2mhz (tcyc=2 s) approx. 64ms at 1mhz (tcyc=4 s) 4.5v to 5.5v/0.92 to 10 s open-drain output (other than p0, p1) (floating) h/l output(p0, p1)with pull-up ffo h is set. 65536 cycles approx. 64ms at 4mhz (tcyc=1 s) lc665xx series(masked rom version) 10 to 40 c c=100pf r=2.7k ? (tool:r=2.2k ? ) c=100pf r=2.2k ? 5.0ma max. (4mhz ceramic resonator oscillation) 6.0ma max. (4mhz external clock source) 5.0ma max. (3mhz typ. rc oscillation) lc6650x series(including tool) dip64s qfp64e not applicable 2.5ma max.(4mhz ceramic resonator oscillation) 3.5ma max.(4mhz external clock source) dip64s qfp64a LC66E516 option-specified output type ffc h is set. dlc64s with window qfc64 with window 2.2v to 5.5v/3.92 to 10 s 3.0v to 5.5v/1.96 to 10 s case outline (package) port output type during reset value(including the value after hold mode release)of timer 0 during reset item differences in system hardware wait time (number of cycles)at hold mode released state external constants for rc oscillation current drain during halt mode on (l dd halt) differences in main characteristics operating supply voltage/operating speed operating free-air temperature (topr) comparison of LC66E516 and the masked rom version(lc665xx)
LC66E516 no.2928 4/18 block diagram pin assignments dic64s with window qfc64 with window
LC66E516 no.2928 5/18 pin function pull-up (pu) mos output type or nch open-drain (od) output type output pin level at reset pin name functional description input/ output data input/output pins (d0 to d3) pch: pull-up (pu) mos type nch: small sink current output type input/output port pins p40 to p43 used for input/output operation in 4-bit units or bit units. these four pins, combined with port pins p50 to p53, can be used for input/output operation in 8-bit units. these four pins, together with port pins p50 to p53, can be used for 8-bit rom data output. i i/o i/o pu mos output type or nch od output type pu mos output type or nch od output type output pin level at reset cmos output type or nch od output type cmos output type or nch od output type i/o input/output port pins p30 to p32 used for input/output operation in 3-bit units or bit units and for input operation in 4-bit units (together with the p33 pin) or bit units. p30 : common with int1 interrupt request input p31 : common with burst pulse output from timer 0 p32 : common with burst pulse output from timer 1 and pwm output pch: cmos type nch: small sink current output type +15v withstand voltage for nch od output hold mode control signal input used for activating hold operation mode with hold = l (active low) by using a hold instruction. used for restarting the cpu operation from the hold mode operation by changing the hold pin level from l to h. used as input port pin p33 to form a 4- bit input port with p30 to p32. the cpu blocks cannot be reset even if the res (active low) pin level changes from h to l, with the hold pin level = l. this means that you cannot write a user application program requiring the p33/hold pin to enter the l level state at the moment the system is powered on. input/output port pins p10 to p13 used for input/output operation in 4-bit units or bit units. input/output port pins p20 to p23 used for input/output operation in 4-bit units or bit units. p20: common with serial input si0 p21: common with serial output so0 p22: common with serial clock sck0 p23: common with int0 interrupt request input, timer 0-used event count input, pulse width measurement input input/output port pins p00 to p03 used for input/output operation in 4-bit units or bit units. used for controlling halt mode operation. pch: cmos type nch: small sink current output type +15v withstand voltage at nch open drain (od) output i/o i/o pch: pull-up (pu) mos type nch: small sink current output type pch: pull-up (pu) mos type nch: small sink current output type pu mos output type or nch od output type pch: pull-up (pu) mos type nch: small sink current output type address input (a11 to a13) i/o p50/a11 p51/a12 p52/a13 p53 input/output port pins p50 to p53 used for input/output operation in 4-bit units or bit units. these four pins, combined with port pins p40 to p43, can be used for input/output operation in 8-bit units. these four pins, together with port pins p40 to p43, can be used for 8-bits rom data output. data input/output pins (d4 to d7) address input (a0 to a3) address input (a7 to a10) address input (a4 to a6) p00/d0 p01/d1 p02/d2 p03/d3 p40/a7 p41/a8 p42/a9 p43/a10 during eprom mode operation option output driver circuit output type p30/int1/a4 p31/pout0/a5 p32/pout1/a6 p33/hold p10/d4 p11/d5 p12/d6 p13/d7 p20/sl0/a0 p21/so0/a1 p22/sck0/a2 p23/int0/a3 continued on next page.
LC66E516 no.2928 6/18 continued from preceding page. o o i/o o i i/o i/o o cmos output type or nch od output type pu mos output type or nch od output type cmos output type or nch od output type input port pins pd0 to pd3 these four pins can be programmed for comparator inputs in user application programs. pd0 input will be compared with vref0. other inputs will be compared with vref1. please note that there are four comparators available in this system and these four comparators are grouped into two (one group: cmp0 and cmp1. the other group: cmp2 and cmp3), and that the comparators must be selected in group units. pch: cmos type nch: small sink current type output port pins pb0 to pb3 used for output operation in 4-bit units or bit units. if you use an input-related instruction in your application program, the content of the output latch will be read in. pch: cmos type nch: small sink current type output port pins pa0 to pa3 used for input operation in 4-bit units or bit units. if you use an input-related instruction in your application program, the content of the output latch will be read in. input/output port pins pc0 to pc3 used for input/output operation in 4-bit units or bit units. pc2: common with vref0 comparator comparison voltage terminal pc3: common with vref1 comparator comparison voltage terminal output port pins p70 to p73 used for output operation in 4-bit units or in bit units. if you use an input-related instruction in your application program, the content of the output latch will be input. input/output port pins p90 to p93 used for input/output operation in 4-bit units or bit units. p90: common with int2 interrupt request input p91: common with int3 interrupt request input p92: common with int4 interrupt request input p93: common with int5 interrupt request input output port pins p80 to p83 used for output operation in 4-bit units or bit units. if you use an input-related instruction in your application program,the content of the output latch will be read in. pch od output type optionally available. more about this later. pch: pull-up (pu) mos type nch: medium sink current output type +15v withstand voltage for nch od output type input/output port pins p60 to p63 used for input/output operation in 4-bit units or bit units. p60: common with serial input si1 p61: common with serial output so1 p62: common with serial clock sck1 p63: common with timer 1-used event count input pch: cmos type nch: small sink current output type +15v withstand voltage for nch od output pch: cmos type nch: small sink current type cmos output type or pch od output type output pin level at reset pch: pull-up (pu) mos type nch: medium sink current type +15v withstand voltage for nch od output type pch: pull-up (pu) mos type nch: medium sink current type pu mos output type or nch od output type eprom controi signal inputs (oe and ce) eprom control signal inputs (prs and pgm) i input port pins pe0 to pe1 these two tristate input port pins can be controlled in your application programs. during eprom mode operation pe0/tra/ce pe1/trb/oe option functional description input/ output pin name cmos output type or nch od output type pd0/cmp0 pd1/cmp1 pd2/cmp2/prs pd3/cmp3/pgm pu mos output type or nch output type output driver circuit output type p60/si1 p61/so1 p62/sck1 p63/pin1 pb0 pb1 pb2 pb3 pc0 pc1 pc2/vref0 pc3/verf1 pa0 pa1 pa2 pa3 p70 p71 p72 p73 p90/int2 p91/int3 p92/int4 p93/int5 p80 p81 p82 p83 continued on next page.
LC66E516 no.2928 7/18 continued from preceding page. input port pin for cpu test signal this pin should be connected with the vss pin when this device is in operation. during eprom mode operation ceramic resonator oscillation. rc oscillation or external clock source option input port pin for system reset request signal to initialize the cpu, the res (active low) pin level must be l with the p33/ hold pin level = h. pins for connecting system clock oscillator externally. if external clock source mode is to be employed, use the osc1 pin only for clock input. leave the other pin open. i o i i power supply pin output driver circuit output type pin name v dd vss functional description input/ output test/v pp osc1 osc2 res condition schmitt trigger input option name selectable oscillation circuit 1. external clock source schmitt trigger input 2. 2-pin (osc1 and osc2) rc oscillation circuit 3. ceramic resonator oscillation circuit option name 1. "h" output level condition in 4-bit units in 4-bit units 2. "l" output level remarks: pu mos type output --- pch mos type transistor acts as a pull-up resistor when data is output. cmos type output --- pch mos type transistor does not act as a pull-up resistor when data is output. instead, it forms a complementary-symmetry mos output circuit with an nch mos type transistor. od output --- open drain output type note: at the system reset, the pin output level of each of input/output and output port pins will be "h" except for such pins as ports 0, 1 and 8. the output level of these exceptions can be specified by the user options. in addition to this system reset operation, the port output type will be set to open drain at the system reset, which is irrespective of user option specifica- tion. in this case, there is no exception. user options 1. option for specifying the output level of ports 0, 1 and 8 at the system reset the output level of ports 0, 1 and 8 at the system reset can be selected from the following two optional levels by the user option. in this case, it should be kept in mind that the output levels of all the four bits of each input/output port are specified at the same time. 2. option for selecting oscillation circuit
LC66E516 no.2928 8/18 3. option for selecting watchdog timer function this option permits the user to select the watchdog timer function. this function could be helpful in detecting a timeout error from your user application program. 4. option for specifying port output type i) this option permits the user to select a desired port output type of the following ports from the two output types listed in the table below. please note that port output types can be specified in bit units. ports: p0, p1, p2, p3 (p33/hold not included), p4, p5, p6, p7, p9, pa, pb, and pc selected output circuit type option name condition ports p7, pa and pb are provided exclusively for output operation. ports p2, p3, p6 and p9 employ schmitt trigger input. 1. open drain output type ports p7, pa and pb are provided exclusively for output operation. ports p2, p3, p6 and p9 employ schmitt trigger input. the pch type mos transistor can act as either a pull-up resistor (for pu mos output circuit) or an output transistor (cmos output circuit), which depends on its driving capability. cmos output type: p2, p3, p6, p9 and pc. pu mos output: p0, p1, p4, p5, p7, pa and pb. 2. pull-up transistor output type selected output circuit type option name condition 1. option drain output type (pch od) 2. pull-down resistor output type ii) the output type of p8 can be selected from the following two options. please note that the output types for the port pins can be specified in bit units. iii) comparator input of the pd and tristate input of the pe can be specified in your user application program. user option specification to select desired user options, you must write appropriate data into the user option specification area in the on-chip eprom. the user option specification will be discussed in detail on the following pages.
LC66E516 no.2928 9/18 how to write data in the user option specification area and the program area in the on-chip eprom (1) writing option codes to the user option specification area use the cross assembler for the lc66516 mask programmed rom-version microcontroller when you write option codes in the user specification area. when your source application program is assembled, the option data will be stored in the user option specification area (3ff8 through 3fff). in addition to the above writing, you are allowed to write option data directly into the user option specification area in the on-chip eprom. in this case, making refer- ences to the option code specification list on the next page will be a "must". (2) writing program into the on-chip eprom program area an eprom writer available on your local market can be used to write program into the on-chip eprom program area. in this case, the eprom writer (27128 eprom writer) must be used together with the dedicated writer board because the pin conversion (64 into 28) is required. the dedicated writer board is shown below. please note that the eprom writer must be either an advantest product or the eva800/850 accessory writer. such an eprom writer enables you to write your application program into the eprom in intel high-speed writing method. model manufacturer advantest eva850 or eva800 accessory eprom writer sanyo tr4943, r4944a, r4945 or equivalent this dedicated writer board is inserted into the eprom writer available on your local market. (select either an advantest writer product or the eva800/850 acces- sory eprom writer). (3) how to erase the contents of the on-chip eprom to erase the contents of the on-chip eprom, you can use an eprom eraser available on your local market. notes 1. intel is a registered trademark of intel corporation. 2. advantest is a registered trademark of advantest corporation.
LC66E516 no.2928 10/18 option code specification list remarks: pu --- pull-up mos type resistance output pd --- pull-down mos type resistance output od --- open-drain output note: the pull-up mos type resistance output represents the pull-up mos (pu mos) type resistor output circuit and the complementary mos (cmos) type output circuit. 6 7 output level at the system reset 0 p01 5 2 1 4 3 oscillation circuit type watchdog timer function option p11 p10 p0 p02 p03 p12 p1 p8 unused unused 2 1 0 4 3 4 5 5 7 6 0 4 5 6 3 6 7 2 7 1 p30 p91 p90 p92 p82 p83 p93 p61 p62 p63 p60 p81 pa2 pa3 pa1 pa0 p00 p80 pb2 pb1 pb0 pb3 p23 p21 p22 p20 p52 p53 3 p32 p33 p31 p50 p72 p73 p71 p51 p40 p43 p70 p42 p41 p13 bit output circuit type option data and selections rom address always set to "0". 3ffbh 3ff8h 3ffah 1: ceramic resonator oscillation. 0: rc oscillation or external clock source 1: selected. 0: not selected. 3ff9h output circuit type 1="h" level, 0="l" level output circuit type output circuit type 3ffch output circuit type output circuit type always set to "0". output circuit type output circuit type optional item 3ffdh 1=pd, 0=od 1=pu, 0=od 1=pu, 0=od 1=pu, 0=od 1=pu, 0=od 1=pu, 0=od 1=pu, 0=od 1=pu, 0=od 1=pu, 0=od 1=pu, 0=od pc0 0 3fffh 3ffeh 1=pu, 0=od always set to "0". output circuit type 1=pu, 0=od 1=pu, 0=od 2 3 4 5 7 6 1 0 7 0 2 2 7 0 output circuit type 6 4 3 6 1 5 1 pc2 pc1 2 1 pc3 output circuit type output circuit type 3 output circuit type unused 1 3 5 4 4 2 0 5 6 7
LC66E516 no.2928 11/18 4 0.2 to v dd +0.3 0.3 to v dd +0.3 0.3 to +15.0 0.3 to +7.0 0.3 to +15.0 75 75 25 25 20 2 4 i op (2) i op (1) i on (1) i op (1) i on (2) i on (2) i on (1) v in (1) v dd v in (2) v dd v out (1) v out (2) all the pins other than the above. p2, p3 (except p33/hold) and p6. p0, p1, p9, pa, pb, pc p0, p1, p9, pa, pb, pc p2, p3 (except p33/hold), p4, p5, p6, p7 and p8. 600 p2, p3 (except p33/hold), p4, p5, p6, p7 and p8. ta=10 to 40 c dic-64s p7, pa, pb i op (2) p2, p3 (except p33/hold), p6, p8, p9 and pc. p2,p 3 (except p33/hold), p6, p7 and pa. p0, p1, p2, p3 ( except p33/hold), p4, p5, p6,p8,p9 and pc. all the pins other than the above p0, p1, p4, p5, p7, pa, pb 4 tstg c 55 to +125 storage temperature output voltage operating temperature output current per pin input voltage allowable power dissipation pin total current 2 2 3 pd max 1 supply voltage 1 4 4 3 3 4 3 ma ma ma ma ma ma ma topr 10 to 40 c mw v ma conditions unit ratings pins applicable and related information symbol note parameter v v v v +13.5 typ v dd (v) min max 5.5 5.5 v ih (1) v dd v ih (3) v ih (2) v dd v dd (h) v dd with output nch transistor "off" 4.5 1.8 0.75v dd po, p1, p4, p5, pc, pd, pe 4.5 to 5.5 p33/hold, p9 res osc1 4.5 to 5.5 with output nch transistor "off" 0.75v dd v dd with hold mode "on" p2, p3(except p33/ hold) and p6. 5.0 v ih (4) pe with tristate input mode selected 0.8v dd 4.5 to 5.5 operating supply voltage input high-level voltage memory backup voltage v 2 1 3 with output nch transistor "off" v dd parameter v symbol v v v 4.5 to 5.5 0.7v dd v dd ratings conditions pins applicable v unit note note 1: applicable only to the pins with open drain output circuit. otherwise, refer to the values listed in the "all the pins other than the above" column. note 2: as far as oscillation input and output are concerned, the voltage range can cover the self-oscillating level. note 3: sink current. as far as the p8 is concerned, these parameters can apply only to the cmos output circuit. note 4: source current. apply to the both of the pull-up output circuit and the cmos output circuit except for p8. allowable operating conditions at ta = 10 ? c to 40 c, v ss =0v, unless otherwise noted continued on next page. specifications absolute maximum ratings at ta = 25 ? c, v ss =0v
LC66E516 no.2928 12/18 note 1: these values apply to the case where the open-drain circuit type has been specified. note that the p33/hold pin is not included (refer to the values listed in v ih (2) column and that the pins p2, p3 and p6 cannot be used as the input pins as far as the cmos output circuit type has been employed. note 2: these values apply to the case where the open drain circuit type has been selected. note that the pin p9 cannot be used as the input pin as far as the cmos type output circuit has been employed. note 3: when the pin pe has been selected as the tristate input pin, the values listed in the v ih (4), v im and v il (4) columns should apply to the pin. note that the pin pc cannot be used as the input pin as far as the cmos type output circuit has been employed. osc1 textr textf osc1, osc2 texth textl f cf refer to figure 2. pe 4.5 to 5.5 4mhz p33/hold p2, p3(except p33/ hold), p6, p9 and res. osc1 with comparator input mode selected pd, pc2, pc3 4.5 to 5.5 4.0 pe p0, p1, p4, p5, pc, pd, pe, test 0.2v dd min typ max v dd l.5 0.6v dd v dd (v) with tristate input mode selected. 4.5 to 5.5 4.35 (0.92) 0.25v dd 4.35 30 0.25v dd 1.0 0.3v dd vss vss 0.4 (10) vss with output nch transistor "off" with output nch transistor "off" 0.4 4.5 to 5.5 vss 1.8 to 5.5 70 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 0.4v dd please refer to figure 1. as it shows, input clocks reach the osc1 pin from an external clock source and the osc2 pin should be left open. the oscil- lation circuit option should be "external clock input". please refer to figure 1. as it shows, input clocks reach the oscl pin from an external clock source and the osc2 pin should be left open. the oscil- lation circuit option should be "external clock input". please refer to figure 1. as it shows, input clocks reach the osc1 pin from an external clock source and the osc2 pin should be left open. the oscil- lation circuit option should be "external clock input". with tristate input mode selected. 4.5 to 5.5 oscillation frequency external clock input mode self oscillation mode refer to figure 4 cext rext operating frequency (instruction cycle time) external r and c constants osc1, osc2 input low-level voltage conditions pins applicable ratings v im in-phase input voltage intermediate level input voltage parameter 100 2.2 4.5 to 5.5 unit pf k ? symbol ceramic resonator oscillation rise and fall times oscillation stabilization time period refer to figure 3 4mhz 4.5 to 5.5 t cfs v il (1) v il (3) v il (2) v cmm v il (4) frequency fext fop (tcyc) pulse width v v3 v v v v2 ms mhz 10 mhz ( s) mhz ns ns note continued from preceding page.
LC66E516 no.2928 13/18 continued on next page. pc2, pc3, pd, pe pins other than p2, p3, p6, p7, p8 and pa input pins otner than pd, pe, pc2 and pc3 pd, pe, pc2, pc3 po, p1, p2, p3, p4, p5, p6, p8, p9 and pc (except p33/ hold). p2, p3, p6, p7, pa p7, pa, pb p0, p1, p4, p5, p7, pa, pb v in = v dd with output nch transistor "off" p0, p1, p4, p5, p7, pa, pb p0, p1, p4, p5, p9, pc, osc1, res and p33/ hold. note that the pd, pe, pc2, and pc3 are not included. 4.5 to 5.5 p2, p3(except p33/ hold), p6, p8, p9, and pc. 0.4 1.5 p8 1.0 1.0 5.0 4.5 to 5.5 v in = 1.0v to v dd l.5v pd 0.5v dd 300 0.75v dd 4.5 to 5.5 1.0 4.5 to 5.5 1.6 v dd 1.0 v dd 0.5 v dd 1.35 4.5 to 5.5 2.4 4.5 to 5.5 4.5 to 5.5 0.1v dd 50 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 5.5 1.0 4.5 4.5 to 5.5 1.0 v in = vss v in = 13.5v v in = v dd i ol = 10ma i oh = 200 a v in = vss with output nch transistor "off" v in = v dd with output nch transistor "off" v in = vss with output nch transistor "off" 4.5 to 5.5 i ol = 1.6ma i oh = 130 a i oh = 1ma v in = vss 1.0 i oh = 0.1ma input low-level current output high-level voltage output low-level voltage output pull-up current input high-level current parameter symbol comparator offset current rc oscillation frequency range f rc schmitt characteristics pins applicable output-off leakage current v a a osc1, osc2 a 1 conditions ratings 1 unit 1 4.0 4 5 a 6 6 2 4 2 3 3 4 7 mhz v 2.0 4.5 to 5.5 3.0 refer to figure 4. c =100pf 5% r = 2.2k ? 1% v oh (1) v oh (2) i po i il (2) i il (1) i ih (3) i off (3) i off (2) v off i off (1) v ol (2) v ol (1) max typ a i ih (2) min 5.0 i ih (1) p2, p3(except p33/ hold) and p6. 4.5 to 5.5 v dd (v) v in = 13.5v with output nch transistor "off" 0.5v dd mv a v v a v v ma a v v low-level threshold voltage vt l high-level threshold voltage hysteresis voltage v hys p2, p3, res, p6, p9, osc1 (rc, ext) 0.25v dd v 4.5 to 5.5 vt h note electrical chracteristics at ta = 10 ? c to 40 c, v ss =0v, unless otherwise noted
LC66E516 no.2928 14/18 continued on next page. continued from preceding page. si0, si1 t cki t cko t ick res t pinh t pinl pin1 t i1h t i1l 2.0 refer to figure 5 (timings). time periods based on the sck0 and sck1 clock rising edges( ). 4.5 to 5.5 0.9 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 t i0h t i0l 0.1 0.3 s t cyc t cyc 3 with reset request acceptable 8 30 4.5 1.0 0.3 0.4 with interrupt request inputs acceptable 4.5 to 5.5 4.5 to 5.5 0.3 s 4 mhz ceramic resonator oscillation data output tckl tckh 4 mhz external clock source refer to figure 5 (timings) and figure 6 (test load). time period based on the sck0 and sck1 clock falling edges( ). with event counter (timer 1) input acceptable t ckr t ckf data input data output data output so0, so1 with into interrupt request input acceptable. with event counter (timer 0) input or pulse width measuring input acceptable. int0 int1, int2, int3, int4, int5 2 2 4.5 to 5.5 2 pins applicable serial input serial timing clock symbol comparator response speed conditions pulse input conditions serial output note ratings s current drain during basis operation mode unit s 8 i dd op rc oscillation 4.5 to 5.5 v dd ma 4.0 8 parameter data hold time rise and fall time res high-level and low-level pulse width low-level and high- level pulse width output delay time high-level and low-level pulse width (into not included) pin1 high-level and low-level pulse width cycle time int0 high-level and low-level pulse width data setup time min typ v dd (v) s max 4.5 to 5.5 t ckcy sck0, sck1 refer to figure 5 (timings) and figure6 (test load). data input t rsh t rsl ma ma t cyc s s t cyc t cyc t cyc 11 pd refer to figure 8. refer to figure 7.- t rs 6.5 4.5 to 5.5
LC66E516 no.2928 15/18 continued from preceding page. i ddhalt v dd 4.5 to 5.5 2.5 v dd (v) 4 mhz ceramic resonator oscillation 4 mhz external clock source rc oscillation 2.5 4.5 max min 3.5 typ 6.0 4.5 1.8 to 5.5 0.01 v dd i ddhold 10 a parameter unit limits current drain during hold operation mode ma conditions ma ma pin applicable current drain during halt operation mode symbol note note 1: applicable to the case where input/output common ports have been set to open-drain output circuit type and the output nch transistors have been in off state. note that the input/output common ports cannot be used as the input port if they have been set to the cmos output circuit type. note 2: applicable to the case where input/output common ports have been set to open-drain output circuit type and the output nch transistors have been in off state. if the pull-up transistor output circuit type has been employed, please refer to the value listed in the output pull-up current column (ipo). note that input/output common ports cannot be used as the input ports if they have been set to the cmos output circuit type. note 3: applicable to the case where the ports have been set to the cmos output circuit type and the output nch transistors have been in off state. also applicable to the p8 pin as far as it has been set to the pch open-drain output circuit type. note 4: applicable to the case where the ports have been set to the pull-up resistor output circuit type and the output nch transistors have been in off state. note 5: applicable to the case where the p8 pin has been set to the cmos output circuit type. note 6: applicable to the case where the ports have been set to the open-drain output circuit type and the output nch transistors have been in off state. note 7: applicable to the case where the port has been set to the open-drain output circuit type and the output pch transistor has been in off state. note 8: reset mode. figure 1. external clock input waveform figure 2. ceramic resonator oscillation circuit figure 3. oscillation stabilization time
LC66E516 no.2928 16/18 table 1. ceramic resonator oscillation constants (recommended) figure 5. serial input/output timings c2 33pf 10% 33pf 10% 33pf 10% c2 c1 4 mhz (kyocera) kbr4.0ms c1 capacitance (internal) 4 mhz (kyocera) kbr 4.0mes 4 mhz (murata) cst4.00mg 33pf 10% capacitance (external) 4 mhz (murata) csa4.00mg figure 6. timing load figure 4. rc oscillation figure 7. input timings for int0, int1, int2, int3, int4, int5, pin1 and res
LC66E516 no.2928 17/18 figure 8. comparator response speed (trs) and output timing figure 9. rc oscillation frequency reference values LC66E516 rc oscillation characteristics figure 9 shows the rc oscillation characteristics of the LC66E516 microcontroller. the rc oscillation frequency range that can be guaranteed is shown below with the external constants and other condi- tions: 2.0mhz frc 4.0mhz external constants --- cext = 100pf and rext = 2.2k ? ta = 10 c to 40 c and v dd = 4.5v to 5.5v if you are to employ the external constants other than the above, the rext and the cext should be within the range between t.b.d k ? and t.b.d k ? , and between t.b.d pf and t.b.d pf, respectively. please take a close look at the figure below. note 10: with v dd = 4.5v to 5.5v and ta = 10 c to 40 c, the oscillation frequency to be selected should meet the requirement that the operating frequencies in the range between 0.4mhz and 4.3mhz must be provided without fail. < = < =
specifications of any and all sanyo products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. sanyo electric co., ltd. strives to supply high-quality high-reliability products. however, any and all semiconductor products fail with some probability. it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo products(including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo electric co. , ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the "delivery specification" for the sanyo product that you intend to use. information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. this catalog provides information as of october, 2001. specifications and information herein are subject to change without notice. LC66E516 no.2928 18/18 series lineup 4k/6k/8kb 512w dip42s qfp48e 42 42 512w dip42s qfp48e 512w 64 512w 42 42 42 42 64 42 512w 64 42 64 42 6k/8kb 6k/8k/12k/16kb 4k/6k/8kb 64 eprom 8kb 12k/16kb 4k/6k/8kb 4k/6k/8kb 6k/8k/12k/16kb otprom 8kb 4k/6k/8kb 512w 512w 512w 512w 512w 512w otprom 8kb eprom 8kb 512w 512w lc66506b/508b/512b/516b lc66e408 lc66562b/566b lc66556b/558b lc66p308 lc66e308 lc66354b/356b/358b lc66354a/356a/358a lc66404a/406/408a lc66556a/558a/562a/566a lc66354s/356s/358s * low voltage version 2.2 to 5.5v/0.92 s dip64s qfp64e evaluation-use windowed version & one-time version 4.5 to 5.5v/0.92 s * :with window low voltage high-speed version 3.0 to 5.5v/0.92 s 512w lc66304a/306a/308a 64 lc66p516 otprom 16kb LC66E516 lc66p408 normal version 4.0 to 6.0v/0.92 s dip42s qfp48e dic42s * qfc48 * dip64s qfp64e dip64s qfp64e dip42s qfp48e 512w dic64s * qfc64 * type number dic42s * qfc48 * dip42s qfp48e dip64s qfp64e ram cap qfp44m pins package rom capacity dip42s qfp48e dip64s qfp64a features eprom 16kb *note : under develoment

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